Recently, numerous innovative power-dissipation-reduction techniques have been used in semiconductor devices. Some of these are listed below:
Dynamic voltage scaling (DVS): The dynamic power that's dissipated by a semiconductor device is proportional to the square of the applied power-supply voltage. DVS techniques are therefore a very effective way of reducing that dynamic power. These techniques consist of applying the lowest voltage to a circuit just enough for it to perform the required system tasks. Dynamically adjusting the applied voltage to the semiconductor device optimizes its power consumption to the required workload. This step is fundamental to extending battery life in deeply embedded systems like today's cell phones. Keep in mind that the effective use of DVS techniques requires an intelligent power supply that's controlled by monitoring-activity software and hardware components. Normally, these techniques are used in conjunction with dynamic frequency scaling (DFS).
Dynamic frequency scaling: The dynamic power that's dissipated by a semiconductor device is proportional to the frequency of the clock signal that's applied to it. It would be inefficient to run a device like a cell phone (which has a required workload that varies immensely over time) at the fixed clock frequency that's needed for performing the highest supported workload. To optimize the power dissipation of the overall system, just adjust the clock frequency that's applied to a device to satisfy the application service's deadlines. Once again, software- and hardware-based intelligent clock controllers are required for applying effective DFS techniques. If the voltage and frequency-dynamic-scaling (DVFS) techniques are combined, the system will operate at the minimal supply voltage and clock frequency that are needed to perform the required services. This approach is one of the most effective strategies for optimizing active, dynamic power dissipation.
Power-island support: When DVFS techniques are applied to subsystems, they create islands within the running system with their own clock and supply-voltage combinations. These subsystems are optimized to the specific workload for that section of the product. A more complex and intelligent power- and clock-controller block is now required. A power-consumption cost exists for getting in and out of a clock/supply-voltage combination. To guarantee an optimal power-consumption profile, the system must be carefully partitioned into power islands in the early phases of development.
Multiple-voltage-threshold (Vt) CMOS: The leakage power of a CMOS circuit comes from several sources. One of the main sources is sub-threshold leakage current, which exponentially increases with the reduction of the CMOS transistors' threshold voltage (Vt). Similarly, the performance of the CMOS transistors increases with the reduction of their Vt. Multiple-threshold CMOS circuits, which combine both high- and low-threshold transistors in a single chip, are used to handle the leakage-power-dissipation problem in battery-operated but high-performance applications like feature-rich cellular phones. Several techniques have been applied, including dual-threshold CMOS and adaptive body biasing (ABB).
Dual-threshold CMOS: When a system's logic partitioning is being implemented, high-Vt transistors are used in non-critical paths. They reduce leakage power dissipation. In contrast, low-Vt transistors are used to handle the performance level that's required in critical paths. This technique is effective for reducing leakage during both active and standby modes.
Adaptive body biasing (ABB): To achieve variable threshold voltages for a system's logic portion, this technique biases the device substrates. In standby mode, adaptive-reverse body bias is applied to increase the device's threshold voltage while reducing leakage current. In active mode, no bias or forward biasing is applied to handle the required performance levels. ABB techniques are a more effective way of reducing the leakage current when compared to DVS techniques. After all, they reduce leakage exponentially rather than linearly (as DVS does).
Deep-sleep modes with logic-state retention: These techniques are used to selectively power down certain regions of a logic block within a system. At the same time, the ABB and DVS techniques are applied to other regions for logic-state retention. These techniques are applied to basic logic elements as sequential logic cells (flip-flops and registers) and memory blocks. They provide very effective power-dissipation-reduction results. At the same time, they save processing energy and silicon real estate when compared to traditional, software-based, state-saving procedures.
Dynamic voltage scaling (DVS): The dynamic power that's dissipated by a semiconductor device is proportional to the square of the applied power-supply voltage. DVS techniques are therefore a very effective way of reducing that dynamic power. These techniques consist of applying the lowest voltage to a circuit just enough for it to perform the required system tasks. Dynamically adjusting the applied voltage to the semiconductor device optimizes its power consumption to the required workload. This step is fundamental to extending battery life in deeply embedded systems like today's cell phones. Keep in mind that the effective use of DVS techniques requires an intelligent power supply that's controlled by monitoring-activity software and hardware components. Normally, these techniques are used in conjunction with dynamic frequency scaling (DFS).
Dynamic frequency scaling: The dynamic power that's dissipated by a semiconductor device is proportional to the frequency of the clock signal that's applied to it. It would be inefficient to run a device like a cell phone (which has a required workload that varies immensely over time) at the fixed clock frequency that's needed for performing the highest supported workload. To optimize the power dissipation of the overall system, just adjust the clock frequency that's applied to a device to satisfy the application service's deadlines. Once again, software- and hardware-based intelligent clock controllers are required for applying effective DFS techniques. If the voltage and frequency-dynamic-scaling (DVFS) techniques are combined, the system will operate at the minimal supply voltage and clock frequency that are needed to perform the required services. This approach is one of the most effective strategies for optimizing active, dynamic power dissipation.
Power-island support: When DVFS techniques are applied to subsystems, they create islands within the running system with their own clock and supply-voltage combinations. These subsystems are optimized to the specific workload for that section of the product. A more complex and intelligent power- and clock-controller block is now required. A power-consumption cost exists for getting in and out of a clock/supply-voltage combination. To guarantee an optimal power-consumption profile, the system must be carefully partitioned into power islands in the early phases of development.
Multiple-voltage-threshold (Vt) CMOS: The leakage power of a CMOS circuit comes from several sources. One of the main sources is sub-threshold leakage current, which exponentially increases with the reduction of the CMOS transistors' threshold voltage (Vt). Similarly, the performance of the CMOS transistors increases with the reduction of their Vt. Multiple-threshold CMOS circuits, which combine both high- and low-threshold transistors in a single chip, are used to handle the leakage-power-dissipation problem in battery-operated but high-performance applications like feature-rich cellular phones. Several techniques have been applied, including dual-threshold CMOS and adaptive body biasing (ABB).
Dual-threshold CMOS: When a system's logic partitioning is being implemented, high-Vt transistors are used in non-critical paths. They reduce leakage power dissipation. In contrast, low-Vt transistors are used to handle the performance level that's required in critical paths. This technique is effective for reducing leakage during both active and standby modes.
Adaptive body biasing (ABB): To achieve variable threshold voltages for a system's logic portion, this technique biases the device substrates. In standby mode, adaptive-reverse body bias is applied to increase the device's threshold voltage while reducing leakage current. In active mode, no bias or forward biasing is applied to handle the required performance levels. ABB techniques are a more effective way of reducing the leakage current when compared to DVS techniques. After all, they reduce leakage exponentially rather than linearly (as DVS does).
Deep-sleep modes with logic-state retention: These techniques are used to selectively power down certain regions of a logic block within a system. At the same time, the ABB and DVS techniques are applied to other regions for logic-state retention. These techniques are applied to basic logic elements as sequential logic cells (flip-flops and registers) and memory blocks. They provide very effective power-dissipation-reduction results. At the same time, they save processing energy and silicon real estate when compared to traditional, software-based, state-saving procedures.
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